1. Field of the Invention
This invention relates to methods of manufacture of select transistors for flash memory cells and more particularly to alignment techniques employed in forming such cells.
2. Description of Related Art
The channel length of a select transistor in current split-gate flash memory cells is equal to the length of word-line (control gate electrode) minus the overlap of the word line and the floating gate electrode. Misalignment during the process of using photolithography to define a split gate electrode pattern can seriously affect the channel length and cause large variations in cell characteristics. This is the major factor which limits the scalability of split-gate flash memory cells. It is difficult to scale down due to the variability of channel length referred to hereinafter as L2.
U.S. Pat. No. 5,385,856 of Hong shows a method of forming a fieldles split gate.
U.S. Pat. No. 5,047,816 of Cuebas shows a self-aligned dual gate transistor method.
U.S. Pat. No. 5,408,115 of Chang and U.S. Pat. No. 5,242,848 of Yeh show other self-aligned methods.